Fast inverter circuits are required in many electronic circuit applications. A typical CMOS inverter circuit is shown in FIG. 1. In this inverter, the input signal voltage, V.sub.in, is applied through input terminal 8 to gate terminals 10 and 20 of PMOS FET 12 and NMOS FET 22, respectively. Source terminal 14 of PMOS FET 12 is connected to supply voltage V.sub.DD and drain terminal 16 of PMOS FET 12 is connected both to drain terminal 24 of NMOS FET 22 and to inverter output terminal 26. Source terminal 28 of NMOS FET 22 is connected to ground.
When the input signal voltage, V.sub.in, on input terminal 8 is at a logic low level, both gates 10 and 20 are low. As a result of these gate voltages, NMOS FET 22 is less conductive than PMOS FET 12. Output terminal 26 is thus set to a logic high level. Conversely, when the input signal voltage, V.sub.in, on input terminal 8 is set high, both gates 10 and 20 are set high and as a result, PMOS FET 12 is less conductive than NMOS FET 22. Output terminal 26 is thus set to logic low. This inverter circuit has a low propagation delay, generally on the order of 3 to 5 nanoseconds.
It should be noted that when the input signal voltage V.sub.in is equal to zero, NMOS FET 22 is shut off and current I.sub.DD from V.sub.DD to ground is zero. Similarly, when V.sub.in is equal to V.sub.DD, PMOS FET 12 is shut off, and current I.sub.DD from V.sub.DD to ground is again zero.
The threshold voltage, corresponding to the input signal voltage about which the inverter output signal transitions, is given by the expression: ##EQU1## where KP.sub.N and KP.sub.P is the transconductance of the N material and P material, respectively, (defined as the mobility of the carrier times the permittivity of the oxide layer divided by the thickness of the oxide layer); (W/L).sub.N and (W/L).sub.P is the ratio of the effective channel width to effective channel length for the NMOS FET and PMOS FET, respectively, and VT.sub.T.sbsb.P and VT.sub.T.sbsb.N is the threshold voltage of the PMOS and NMOS, respectively. More particularly, when the input signal voltage V.sub.in satisfies equation (1) above, the drain-to-source current of the NMOS FET 22 is equal to the drain-to-source current of the PMOS FET 22 (i.e., ID.sub.DS.sbsb.N =I.sub.DS.sbsb.P) and NMOS FET 22 and PMOS FET 12 are in saturation.
Although this prior art inverter has the attributes of having a small size and a low propagation delay, the threshold voltage, V.sub.threshold, about which the output signal V.sub.out changes state is a function of parameters V.sub.DD, VT.sub.T.sbsb.P, V.sub.T.sbsb.N, KP.sub.P and KP.sub.N and may vary by as much as .+-.25% as a function of process and temperature variations.